make_f22.fcl
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1 process_name: DROPM1A
2 
3 source: {
4  module_type: RootInput
5  fileNames: [ "../test_tiered_input_04a2_t.d/f12.root" ]
6 }
7 
8 outputs: {
9  out1: {
10  module_type: RootOutput
11  fileName: "f22.root"
12  outputCommands: [ "keep *", "drop arttest::IntProduct_m1a__MAKET1" ]
13  }
14 }
15 
16 physics: {
17  e1: [ out1 ]
18 }