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art
art
test
Integration
test_tiered_input_04
fcl
make_f12.fcl
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process_name: MAKET1
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source: {
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module_type: EmptyEvent
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firstEvent: 10
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maxEvents: 8
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}
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outputs: {
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out1: {
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module_type: RootOutput
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fileName: "f12.root"
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}
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}
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physics: {
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producers: {
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m1a: {
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module_type: IntProducer
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ivalue: 1
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}
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m2a: {
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module_type: IntProducer
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ivalue: 2
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}
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m3a: {
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module_type: IntProducer
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ivalue: 3
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}
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}
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p1: [ m1a, m2a, m3a ]
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e1: [ out1 ]
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}
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