make_f2.fcl

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source: {
  module_type: RootInput
  fileNames: [ "../test_tiered_input_05a_t.d/f1.root" ]
}

outputs: {
  out1: {
    module_type: RootOutput
    fileName: "f2.root"
    outputCommands: [ "keep *", "drop arttest::IntProduct_m1a__MAKEF1" ]
  }
}

physics: {
  e1: [ out1 ]
}

process_name: DROPM1A