27 using std::istringstream;
42 if ( sigdiff < -0.5 || sigdiff > 0.5 ) {
43 cout <<
"sigequal: " << sig1 <<
" != " << sig2 <<
endl;
50 if ( flg1 == flg2 )
return true;
54 cout <<
"flagequal: " << flg1 <<
" != " << flg2 <<
endl;
64 const string myname =
"test_StandardRawDigitPrepService: ";
66 cout << myname <<
"NDEBUG must be off." <<
endl;
69 string line =
"-----------------------------";
71 cout << myname << line <<
endl;
72 cout << myname <<
"Create top-level FCL." <<
endl;
73 bool usePedestalAdjustment =
false;
74 vector<string> snames;
80 else if (useFclFile) {
85 config <<
"#include \"services_dune.fcl\"" <<
endl;
86 config <<
"services: @local::dune35tdata_reco_services" <<
endl;
88 config <<
"services.RawDigitExtractService.LogLevel: 3" <<
endl;
89 config <<
"services.RawDigitPrepService.LogLevel: 3" <<
endl;
90 config <<
"services.RawDigitPrepService.DoDump: true" <<
endl;
91 config <<
"services.RawDigitPrepService.DumpChannel: 0" <<
endl;
93 config <<
"services.RawDigitPrepService.DoNoiseRemoval: false" <<
endl;
94 config <<
"services.RawDigitPrepService.DoDeconvolution: false" <<
endl;
95 config <<
"services.RawDigitPrepService.DoIntermediateStates: true" <<
endl;
96 config <<
"services.AdcChannelDataCopyService.CopyFlags: true" <<
endl;
98 snames.push_back(
"extracted");
99 snames.push_back(
"mitigated");
102 config <<
"#include \"services_dune.fcl\"" <<
endl;
103 config <<
"services: @local::dune35t_services_legacy" <<
endl;
104 config <<
"services.RawDigitExtractService: {" <<
endl;
105 config <<
" service_provider: StandardRawDigitExtractService" <<
endl;
106 config <<
" LogLevel: 1" <<
endl;
107 config <<
" PedestalOption: 1" <<
endl;
108 config <<
" FlagStuckOff: true" <<
endl;
109 config <<
" FlagStuckOn: true" <<
endl;
110 config <<
"}" <<
endl;
111 config <<
"services.AdcMitigationService: {" <<
endl;
112 config <<
" service_provider: InterpolatingAdcMitigationService" <<
endl;
113 config <<
" LogLevel: 1" <<
endl;
114 config <<
" SkipUnderflows: true" <<
endl;
115 config <<
" SkipOverflows: true" <<
endl;
116 config <<
" MaxConsecutiveSamples: 3" <<
endl;
117 config <<
" MaxConsecutiveFlag: 0" <<
endl;
118 config <<
"}" <<
endl;
119 config <<
"services.PedestalEvaluationService: {" <<
endl;
120 config <<
" service_provider: MedianPedestalService" <<
endl;
121 config <<
" LogLevel: 1" <<
endl;
122 config <<
" SkipFlaggedSamples: true" <<
endl;
123 config <<
" SkipSignals: true" <<
endl;
124 config <<
"}" <<
endl;
125 config <<
"services.AdcChannelNoiseRemovalService: {" <<
endl;
126 config <<
" service_provider: ThresholdNoiseRemovalService" <<
endl;
127 config <<
" Threshold: 10.0" <<
endl;
128 config <<
" LogLevel: 1" <<
endl;
129 config <<
"}" <<
endl;
130 config <<
"services.AdcNoiseRemovalService: {" <<
endl;
131 config <<
" service_provider: MultiChannelNoiseRemovalService" <<
endl;
132 config <<
" LogLevel: 1" <<
endl;
133 config <<
"}" <<
endl;
134 config <<
"services.AdcChannelDataCopyService: {" <<
endl;
135 config <<
" service_provider: ConfigurableAdcChannelDataCopyService" <<
endl;
136 config <<
" LogLevel: 1" <<
endl;
137 config <<
" CopyChannel: true" <<
endl;
138 config <<
" CopyPedestal: true" <<
endl;
139 config <<
" CopySamples: true" <<
endl;
140 config <<
" CopyFlags: true" <<
endl;
141 config <<
" CopyDigit: true" <<
endl;
142 config <<
" CopyDigitIndex: true" <<
endl;
143 config <<
"}" <<
endl;
144 config <<
"services.AdcRoiBuildingService: {" <<
endl;
145 config <<
" service_provider: KeepAllRoiBuildingService" <<
endl;
146 config <<
" LogLevel: 1" <<
endl;
147 config <<
"}" <<
endl;
148 config <<
"services.AdcWireBuildingService: {" <<
endl;
149 config <<
" service_provider: StandardAdcWireBuildingService" <<
endl;
150 config <<
" LogLevel: 1" <<
endl;
151 config <<
"}" <<
endl;
152 config <<
"services.RawDigitPrepService: {" <<
endl;
153 config <<
" service_provider: StandardRawDigitPrepService" <<
endl;
154 config <<
" LogLevel: 1" <<
endl;
155 config <<
" SkipBad: false" <<
endl;
156 config <<
" SkipNoisy: false" <<
endl;
157 config <<
" DoMitigation: true" <<
endl;
158 config <<
" DoEarlySignalFinding: false" <<
endl;
159 config <<
" DoNoiseRemoval: true" <<
endl;
160 config <<
" DoDeconvolution: false" <<
endl;
161 config <<
" DoROI: true" <<
endl;
162 config <<
" DoWires: true" <<
endl;
163 config <<
" DoPedestalAdjustment: false" <<
endl;
164 config <<
" DoIntermediateStates: true" <<
endl;
165 config <<
"}" <<
endl;
167 usePedestalAdjustment =
false;
168 snames.push_back(
"extracted");
169 snames.push_back(
"mitigated");
170 snames.push_back(
"noiseRemoved");
176 cout << myname << line <<
endl;
177 cout << myname <<
"Create raw digits." <<
endl;
179 unsigned int nsig = 64;
182 unsigned int isig_stucklo = 15;
183 unsigned int isig_stuckhi = 25;
185 AdcSignal peds[8] = {2000.2, 2010.1, 2020.3, 1990.4, 1979.6, 1979.2, 1995.0, 2001.3};
186 AdcSignal xpeds[8] = {0, 0, 0, 0, 0, 0, 0, 0};
187 if ( usePedestalAdjustment ) {
193 vector<RawDigit> digs;
194 map<AdcChannel, AdcCountVector> adcsmap;
195 map<AdcChannel, AdcFlagVector> expflagsmap;
197 for (
AdcChannel chan=0; chan<nchan; ++chan ) {
198 unsigned int isig1 = 10 + chan;
199 for (
unsigned int isig=0; isig<isig1; ++isig ) sigsin[chan].
push_back(0);
200 for (
unsigned int i=0; i<10; ++i ) sigsin[chan].
push_back(fac*i);
201 for (
unsigned int i=10; i<1000; --i ) sigsin[chan].
push_back(fac*i);
202 for (
unsigned int i=19; i<1000; --i ) sigsin[chan].
push_back(-sigsin[chan][i+isig1]);
203 for (
unsigned int isig=sigsin[chan].
size();
204 isig<nsig; ++isig ) sigsin[chan].
push_back(0);
205 assert(sigsin[chan].
size() == nsig);
207 for (
unsigned int isig=0; isig<nsig; ++isig) {
208 AdcSignal sig = sigsin[chan][isig] + peds[chan] + xpeds[chan];
210 if ( sig > 0.0 ) adc =
int(sig+0.5);
211 if ( adc > 4095 ) adc = 4095;
213 if ( isig == isig_stucklo ) adc = adchigh;
214 if ( isig == isig_stuckhi ) adc = adchigh + lowbits;
215 adcsin.push_back(adc);
217 assert(adcsin.size() == nsig);
218 adcsmap[chan] = adcsin;
222 cout << myname <<
" Compressed size: " << dig.
NADC() <<
endl;
223 cout << myname <<
" Uncompressed size: " << dig.
Samples() <<
endl;
225 cout << myname <<
" Channel: " << dig.
Channel() <<
endl;
230 assert( adcsmap.size() == nchan );
232 cout << myname << line <<
endl;
233 cout << myname <<
"Create the expected flag vector." <<
endl;
234 for (
AdcChannel chan=0; chan<nchan; ++chan ) {
236 for (
unsigned int isig=0; isig<nsig; ++isig) {
240 else if ( adc >= 4095 ) expflags[isig] =
AdcOverflow;
241 else if ( adclow == 0 ) expflags[isig] =
AdcStuckOff;
242 else if ( adclow == lowbits ) expflags[isig] =
AdcStuckOn;
244 expflagsmap[chan] = expflags;
247 cout << myname << line <<
endl;
248 cout << myname <<
"Fetch raw digit prep service." <<
endl;
252 cout << myname << line <<
endl;
253 cout << myname <<
"Prep data from digits." <<
endl;
257 for (
unsigned int idig=0; idig<digs.size(); ++idig ) {
259 assert( prepdigs.find(dig.
Channel()) == prepdigs.end() );
261 data.setChannelInfo(dig.
Channel());
262 data.digitIndex = idig;
265 std::vector<recob::Wire> wires;
266 wires.reserve(nchan);
268 assert( intStates.
dataMaps.size() == snames.size() );
269 assert( intStates.
wires.size() == snames.size() );
271 assert( hrdp->
prepare(clockData, prepdigs, &wires, &intStates) == 0 );
272 cout << myname <<
" # prepared digit channels: " << prepdigs.size() <<
endl;
273 cout << myname <<
" # wire channels: " << wires.size() <<
endl;
274 cout << myname <<
" # intermediate state channels: " << intStates.
dataMaps.size() <<
endl;
275 for (
const auto& namedadm : intStates.
dataMaps ) {
276 string sname = namedadm.first;
278 auto iwco = intStates.
wires.find(sname);
279 const vector<Wire>* pwires =
nullptr;
280 if ( iwco == intStates.
wires.end() ) {
281 cout << myname <<
" Wires not found for intermediate state " << sname <<
"." <<
endl;
282 assert( iwco != intStates.
wires.end() );
284 pwires = iwco->second;
286 assert( pwires !=
nullptr );
287 cout << myname <<
" State " << sname <<
" has " << adm.size() <<
" ADC channels";
288 if ( pwires !=
nullptr ) cout <<
" and " << pwires->size() <<
" wires";
290 assert( pwires->size() == adm.size() );
292 cout << myname <<
" # intermediate wires: " << intStates.
wires.size() <<
endl;
301 cout << myname <<
"----- Channel " << chan <<
endl;
302 cout << myname <<
" Final signal tick count: " << sigs.size() <<
endl;
303 cout << myname <<
" Final flag tick count: " << flags.size() <<
endl;
304 cout << myname <<
" Final flag tick count: " << flags.size() <<
endl;
305 cout << myname <<
" Pedestal: " << ped <<
endl;
306 cout << myname <<
" samples[0]: " << sigs[0] <<
endl;
307 cout << myname <<
"Check final data." <<
endl;
308 assert( pwire !=
nullptr );
310 assert( sigs.size() == nsig );
311 assert( flags.size() == nsig );
312 assert( pdig !=
nullptr );
313 assert( pdig == &digs[chan] );
314 assert( pdig->
Channel() == chan );
315 assert( ichdat->second.digitIndex == chan );
317 assert( expflagsmap[chan].
size() == nsig );
319 cout << myname <<
"Fetch intermediate data." <<
endl;
320 vector<const AdcSignalVector*> intSigs;
321 vector<const AdcFlagVector*> intFlags;
322 cout << myname <<
" ...bad" <<
endl;
323 auto iacd = intStates.
dataMaps.find(
"bad");
324 assert( iacd == intStates.
dataMaps.end() );
325 string header =
" ch-tk raw";
326 unsigned int nintexp = 0;
327 for (
string sname : snames ) {
328 cout << myname <<
" ..." << sname <<
endl;
329 iacd = intStates.
dataMaps.find(sname);
330 assert( iacd != intStates.
dataMaps.end() );
332 intSigs.push_back(&intAcd.samples);
333 intFlags.push_back(&intAcd.flags);
334 assert( intAcd.wire !=
nullptr );
335 for (
unsigned int i=sname.size(); i<12; ++i ) header +=
" ";
338 cout << myname <<
" Checking sample and flag tick counts." <<
endl;
339 assert( intSigs.back() != nullptr );
340 assert( intSigs.back()->size() != 0 );
341 assert( intSigs.back()->size() == nsig );
342 assert( intFlags.back() != nullptr );
343 assert( intFlags.back()->size() != 0 );
344 assert( intFlags.back()->size() == nsig );
345 cout << myname <<
" Wire ROI count: " << intAcd.wire->SignalROI().n_ranges() <<
endl;
346 cout << myname <<
" Wire Tick count: " << intAcd.wire->SignalROI().size() <<
endl;
347 assert( intAcd.wire->SignalROI().n_ranges() == 1 );
348 assert( intAcd.wire->SignalROI().size() == nsig );
351 assert( intStates.
dataMaps.size() == nintexp );
353 assert( intSigs.size() == nintexp );
354 assert( intFlags.size() == nintexp );
356 cout << myname <<
"Display intermediate and final samples." <<
endl;
357 cout << myname << header <<
endl;
358 for (
unsigned int isig=0; isig<nsig; ++isig ) {
360 cout <<
setw(4) << chan <<
"-" 361 <<
setw(2) << isig <<
": " <<
setw(4) << adcsmap[chan][isig];
362 for (
unsigned int ista=0; ista<intSigs.size(); ++ista ) {
364 cout <<
" [" << intFlags[ista]->at(isig) <<
"]";
367 <<
" [" << flags[isig] <<
"]" <<
endl;
368 assert( adcsmap[chan][isig] == acd.
raw[isig] );
369 if ( flags[isig] ==
AdcGood ) assert(
sigequal(sigs[isig], sigsin[chan][isig]) );
370 assert(
flagequal(flags[isig], expflags[isig]) );
374 cout << myname << line <<
endl;
375 cout <<
"Done." <<
endl;
382 bool useExistingFcl =
false;
383 bool useFclFile =
true;
385 string sarg(argv[1]);
386 if ( sarg ==
"-h" ) {
387 cout <<
"Usage: " << argv[0] <<
" [UseExisting] [UseFclFile]" <<
endl;
388 cout <<
" If UseExisting = true, existing FCL file is used [false]." <<
endl;
389 cout <<
" If UseFclFile = true, FCL file dataprep_dune [true]." <<
endl;
392 useExistingFcl = sarg ==
"true" || sarg ==
"1";
395 string sarg(argv[2]);
396 useFclFile = sarg ==
"true" || sarg ==
"1";
float GetPedestal() const
std::vector< AdcCount > AdcCountVector
bool flagequal(AdcFlag flg1, AdcFlag flg2)
ULong64_t Samples() const
Number of samples in the uncompressed ADC data.
Collection of charge vs time digitized from a single readout channel.
size_type size() const
Returns the size of the vector.
static constexpr FileOnPath_t FileOnPath
std::vector< AdcFlag > AdcFlagVector
ChannelID_t Channel() const
DAQ channel this raw data was read from.
const AdcFlag AdcUnderflow
const raw::RawDigit * digit
virtual int prepare(detinfo::DetectorClocksData const &clockData, AdcChannelDataMap &prepdigs, std::vector< recob::Wire > *pwires=nullptr, WiredAdcChannelDataMap *pwiredData=nullptr) const =0
static void load_services(std::string const &config)
Q_EXPORT QTSManip setprecision(int p)
const AdcFlag AdcSetFixed
std::map< Name, AdcChannelDataMap > dataMaps
decltype(auto) constexpr size(T &&obj)
ADL-aware version of std::size.
fInnerVessel push_back(Point(-578.400000, 0.000000, 0.000000))
const AdcFlag AdcOverflow
size_t NADC() const
Number of elements in the compressed ADC sample vector.
bool sigequal(AdcSignal sig1, AdcSignal sig2)
const RegionsOfInterest_t & SignalROI() const
Returns the list of regions of interest.
int main(int argc, char *argv[])
Q_EXPORT QTSManip setw(int w)
std::map< Name, WireContainer * > wires
const AdcFlag AdcStuckOff
std::vector< AdcSignalVector > AdcSignalVectorVector
const AdcFlag AdcInterpolated
void SetPedestal(float ped, float sigma=1.)
Set pedestal and its RMS (the latter is 0 by default)
void line(double t, double *p, double &x, double &y, double &z)
Class holding the regions of interest of signal from a channel.
std::vector< AdcSignal > AdcSignalVector
virtual std::ostream & print(std::ostream &out=std::cout, std::string prefix="") const =0
std::map< AdcChannel, AdcChannelData > AdcChannelDataMap
int test_StandardRawDigitPrepService(bool useExistingFcl=false, bool useFclFile=false)
QTextStream & endl(QTextStream &s)