30 using std::istringstream;
45 if ( sigdiff < -0.5 || sigdiff > 0.5 ) {
46 cout <<
"sigequal: " << sig1 <<
" != " << sig2 <<
endl;
53 if ( flg1 == flg2 )
return true;
57 cout <<
"flagequal: " << flg1 <<
" != " << flg2 <<
endl;
64 const string myname =
"test_TpcToolBasedRawDigitPrepService: ";
66 cout << myname <<
"NDEBUG must be off." <<
endl;
69 string line =
"-----------------------------";
71 cout << myname << line <<
endl;
72 cout << myname <<
"Create top-level FCL." <<
endl;
73 std::string const fclfile{
"test_TpcToolBasedRawDigitPrepService.fcl"};
74 if (!useExistingFcl) {
75 std::ofstream
fout{fclfile};
76 fout <<
"#include \"services_dune.fcl\"" <<
endl;
77 fout <<
"services: @local::dune35t_services_legacy" <<
endl;
78 fout <<
"#include \"tools_dune.fcl\"" <<
endl;
79 fout <<
"services.AdcWireBuildingService: {" <<
endl;
80 fout <<
" service_provider: StandardAdcWireBuildingService" <<
endl;
83 fout <<
"services.RawDigitPrepService: {" <<
endl;
84 fout <<
" service_provider: TpcToolBasedRawDigitPrepService" <<
endl;
90 fout <<
" \"rawAdcPlotter\"," <<
endl;
91 fout <<
" \"adcSampleFiller\"," <<
endl;
92 fout <<
" \"preparedAdcPlotter\"," <<
endl;
93 fout <<
" \"adcThresholdSignalFinder\"" <<
endl;
96 fout <<
" CallgrindToolNames: []" <<
endl;
101 std::ifstream
config{fclfile};
104 cout << myname << line <<
endl;
105 cout << myname <<
"Fetching tool manager." <<
endl;
107 assert ( ptm !=
nullptr );
115 cout << myname << line <<
endl;
116 cout << myname <<
"Create raw digits." <<
endl;
118 unsigned int nsig = 64;
121 unsigned int isig_stucklo = 15;
122 unsigned int isig_stuckhi = 25;
123 bool doSticky =
false;
125 AdcSignal peds[8] = {2000.2, 2010.1, 2020.3, 1990.4, 1979.6, 1979.2, 1995.0, 2001.3};
126 vector<RawDigit> digs;
127 map<AdcChannel, AdcCountVector> adcsmap;
128 map<AdcChannel, AdcFlagVector> expflagsmap;
130 for (
AdcChannel chan=0; chan<nchan; ++chan ) {
131 unsigned int isig1 = 10 + chan;
132 for (
unsigned int isig=0; isig<isig1; ++isig ) sigsin[chan].
push_back(0);
133 for (
unsigned int i=0; i<10; ++i ) sigsin[chan].
push_back(fac*i);
134 for (
unsigned int i=10; i<1000; --i ) sigsin[chan].
push_back(fac*i);
135 for (
unsigned int i=19; i<1000; --i ) sigsin[chan].
push_back(-sigsin[chan][i+isig1]);
136 for (
unsigned int isig=sigsin[chan].
size();
137 isig<nsig; ++isig ) sigsin[chan].
push_back(0);
138 assert(sigsin[chan].
size() == nsig);
140 for (
unsigned int isig=0; isig<nsig; ++isig) {
141 AdcSignal sig = sigsin[chan][isig] + peds[chan];
143 if ( sig > 0.0 ) adc =
int(sig+0.5);
144 if ( adc > 4095 ) adc = 4095;
147 if ( isig == isig_stucklo ) adc = adchigh;
148 if ( isig == isig_stuckhi ) adc = adchigh + lowbits;
150 adcsin.push_back(adc);
152 assert(adcsin.size() == nsig);
153 adcsmap[chan] = adcsin;
157 cout << myname <<
" Compressed size: " << dig.
NADC() <<
endl;
158 cout << myname <<
" Uncompressed size: " << dig.
Samples() <<
endl;
160 cout << myname <<
" Channel: " << dig.
Channel() <<
endl;
165 assert( adcsmap.size() == nchan );
167 cout << myname << line <<
endl;
168 cout << myname <<
"Create the expected flag vector." <<
endl;
169 for (
AdcChannel chan=0; chan<nchan; ++chan ) {
171 for (
unsigned int isig=0; isig<nsig; ++isig) {
175 else if ( adc >= 4095 ) expflags[isig] =
AdcOverflow;
176 else if ( doSticky ) {
178 else if ( adclow == lowbits ) expflags[isig] =
AdcStuckOn;
181 expflagsmap[chan] = expflags;
184 cout << myname << line <<
endl;
185 cout << myname <<
"Fetch raw digit prep service." <<
endl;
189 cout << myname << line <<
endl;
190 cout << myname <<
"Prep data from digits." <<
endl;
194 for (
unsigned int idig=0; idig<digs.size(); ++idig ) {
196 assert( prepdigs.find(dig.
Channel()) == prepdigs.end() );
198 data.setChannelInfo(dig.
Channel());
199 data.digitIndex = idig;
201 data.setEventInfo(123, 1);
203 std::vector<recob::Wire> wires;
204 wires.reserve(nchan);
205 vector<string> snames;
207 assert( intStates.
dataMaps.size() == snames.size() );
208 assert( intStates.
wires.size() == snames.size() );
210 assert( hrdp->
prepare(clockData, prepdigs, &wires, &intStates) == 0 );
211 cout << myname <<
" # prepared digit channels: " << prepdigs.size() <<
endl;
212 cout << myname <<
" # wire channels: " << wires.size() <<
endl;
213 cout << myname <<
" # intermediate state channels: " << intStates.
dataMaps.size() <<
endl;
214 for (
const auto& namedadm : intStates.
dataMaps ) {
215 string sname = namedadm.first;
217 auto iwco = intStates.
wires.find(sname);
218 const vector<Wire>* pwires =
nullptr;
219 if ( iwco == intStates.
wires.end() ) {
220 cout << myname <<
" Wires not found for intermediate state " << sname <<
"." <<
endl;
221 assert( iwco != intStates.
wires.end() );
223 pwires = iwco->second;
225 assert( pwires !=
nullptr );
226 cout << myname <<
" State " << sname <<
" has " << adm.size() <<
" ADC channels";
227 if ( pwires !=
nullptr ) cout <<
" and " << pwires->size() <<
" wires";
229 assert( pwires->size() == adm.size() );
231 cout << myname <<
" # intermediate wires: " << intStates.
wires.size() <<
endl;
240 cout << myname <<
"----- Channel " << chan <<
endl;
241 cout << myname <<
" Final signal tick count: " << sigs.size() <<
endl;
242 cout << myname <<
" Final flag tick count: " << flags.size() <<
endl;
243 cout << myname <<
" Final flag tick count: " << flags.size() <<
endl;
244 cout << myname <<
" Pedestal: " << ped <<
endl;
245 cout << myname <<
" samples[0]: " << sigs[0] <<
endl;
246 cout << myname <<
"Check final data." <<
endl;
247 assert( pwire !=
nullptr );
249 assert( sigs.size() == nsig );
250 assert( flags.size() == nsig );
251 assert( pdig !=
nullptr );
252 assert( pdig == &digs[chan] );
253 assert( pdig->
Channel() == chan );
254 assert( ichdat->second.digitIndex == chan );
256 assert( expflagsmap[chan].
size() == nsig );
258 cout << myname <<
"Fetch intermediate data." <<
endl;
259 vector<const AdcSignalVector*> intSigs;
260 vector<const AdcFlagVector*> intFlags;
261 cout << myname <<
" ...bad" <<
endl;
262 auto iacd = intStates.
dataMaps.find(
"bad");
263 assert( iacd == intStates.
dataMaps.end() );
264 string header =
" ch-tk raw";
265 unsigned int nintexp = 0;
266 for (
string sname : snames ) {
267 cout << myname <<
" ..." << sname <<
endl;
268 iacd = intStates.
dataMaps.find(sname);
269 assert( iacd != intStates.
dataMaps.end() );
271 intSigs.push_back(&intAcd.samples);
272 intFlags.push_back(&intAcd.flags);
273 assert( intAcd.wire !=
nullptr );
274 for (
unsigned int i=sname.size(); i<12; ++i ) header +=
" ";
277 cout << myname <<
" Checking sample and flag tick counts." <<
endl;
278 assert( intSigs.back() != nullptr );
279 assert( intSigs.back()->size() != 0 );
280 assert( intSigs.back()->size() == nsig );
281 assert( intFlags.back() != nullptr );
282 assert( intFlags.back()->size() != 0 );
283 assert( intFlags.back()->size() == nsig );
284 cout << myname <<
" Wire ROI count: " << intAcd.wire->SignalROI().n_ranges() <<
endl;
285 cout << myname <<
" Wire Tick count: " << intAcd.wire->SignalROI().size() <<
endl;
286 assert( intAcd.wire->SignalROI().n_ranges() == 1 );
287 assert( intAcd.wire->SignalROI().size() == nsig );
290 assert( intStates.
dataMaps.size() == nintexp );
292 assert( intSigs.size() == nintexp );
293 assert( intFlags.size() == nintexp );
295 cout << myname <<
"Display intermediate and final samples." <<
endl;
296 cout << myname << header <<
endl;
297 for (
unsigned int isig=0; isig<nsig; ++isig ) {
299 cout <<
setw(4) << chan <<
"-" 300 <<
setw(2) << isig <<
": " <<
setw(4) << adcsmap[chan][isig];
301 for (
unsigned int ista=0; ista<intSigs.size(); ++ista ) {
303 cout <<
" [" << intFlags[ista]->at(isig) <<
"]";
306 <<
" [" << flags[isig] <<
"]" <<
endl;
307 assert( adcsmap[chan][isig] == acd.
raw[isig] );
308 if ( flags[isig] ==
AdcGood ) assert(
sigequal(sigs[isig], sigsin[chan][isig]) );
309 assert(
flagequal(flags[isig], expflags[isig]) );
313 cout << myname << line <<
endl;
314 cout <<
"Done." <<
endl;
321 bool useExistingFcl =
false;
323 string sarg(argv[1]);
324 if ( sarg ==
"-h" ) {
325 cout <<
"Usage: " << argv[0] <<
" [UseExisting]" <<
endl;
326 cout <<
" If UseExisting = true, existing FCL file is used [false]." <<
endl;
329 useExistingFcl = sarg ==
"true" || sarg ==
"1";
331 TH1::AddDirectory(
false);
float GetPedestal() const
std::vector< AdcCount > AdcCountVector
ULong64_t Samples() const
Number of samples in the uncompressed ADC data.
Collection of charge vs time digitized from a single readout channel.
size_type size() const
Returns the size of the vector.
std::vector< AdcFlag > AdcFlagVector
ChannelID_t Channel() const
DAQ channel this raw data was read from.
const AdcFlag AdcUnderflow
const raw::RawDigit * digit
virtual int prepare(detinfo::DetectorClocksData const &clockData, AdcChannelDataMap &prepdigs, std::vector< recob::Wire > *pwires=nullptr, WiredAdcChannelDataMap *pwiredData=nullptr) const =0
static void load_services(std::string const &config)
Q_EXPORT QTSManip setprecision(int p)
const AdcFlag AdcSetFixed
std::map< Name, AdcChannelDataMap > dataMaps
decltype(auto) constexpr size(T &&obj)
ADL-aware version of std::size.
fInnerVessel push_back(Point(-578.400000, 0.000000, 0.000000))
const AdcFlag AdcOverflow
size_t NADC() const
Number of elements in the compressed ADC sample vector.
const RegionsOfInterest_t & SignalROI() const
Returns the list of regions of interest.
Q_EXPORT QTSManip setw(int w)
std::map< Name, WireContainer * > wires
const AdcFlag AdcStuckOff
std::vector< AdcSignalVector > AdcSignalVectorVector
const AdcFlag AdcInterpolated
void SetPedestal(float ped, float sigma=1.)
Set pedestal and its RMS (the latter is 0 by default)
void line(double t, double *p, double &x, double &y, double &z)
Class holding the regions of interest of signal from a channel.
std::vector< AdcSignal > AdcSignalVector
virtual std::ostream & print(std::ostream &out=std::cout, std::string prefix="") const =0
std::map< AdcChannel, AdcChannelData > AdcChannelDataMap
QTextStream & endl(QTextStream &s)